Silicon Photonics Design Framework
We have created a generic design framework that allows rapid setup of files for our Silicon Photonics Remote Foundry services. Using this layout file as a starting point enables us to utilize well-established data processing scripts and exposure Job Decks, which saves us time and saves you money over having to customize these for each job. That said, there are many variations possible on this; some as simple, transparent options, others may require significant changes to our scripting or exposure jobs, and thus many incur significant costs. Please discuss your need with us so we can establish the best methods to achieve your desired results.
The framework is based around exposing a 25 mm square chip of SOI material, with a 3 mm edge exclusion. It is divided into 4 quadrants, each 9x9 mm; each surrounded by process metrology features and e-beam alignment marks capable of supporting up to 3 layers of lithography and etching.
You can download the GDS-II design file here, and a PDF documentation file here.
You can also download a single ZIP archive containing both files here.